Initial commit for basics need a refresher.

This commit is contained in:
2026-04-16 07:34:21 +02:00
parent 67dc2470e0
commit 12c42d9563
5 changed files with 141 additions and 0 deletions

20
internal/bus/bus.go Normal file
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package bus
type MainBus struct {
// add ram etc here
}
func New() *MainBus {
return &MainBus{}
}
// Just a test read for now, need to figure wtf is happening...
func (b *MainBus) Read(address uint16) uint8 {
// Just testing with NOPs
return 0xEA
}
func (b *MainBus) Write(address uint16, data uint8) {
// Need to write data to the actual ram.
}

85
internal/cpu/cpu.go Normal file
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package cpu
import "fmt"
const ARCH = "MOS6502"
// bits for the status register
const (
FlagCarry = 1 << 0 // Bit 0
FlagZero = 1 << 1 // Bit 1
FlagInterrupt = 1 << 2 // Bit 2
FlagDecimal = 1 << 3 // Bit 3
FlagBreak = 1 << 4 // Bit 4
FlagUnused = 1 << 5 // Bit 5
FlagOverflow = 1 << 6 // Bit 6
FlagNegative = 1 << 7 // Bit 7
)
type Bus interface {
Read(address uint16) uint8
}
type CPU struct {
A uint8 // Accumulator
X uint8 // X Register
Y uint8 // Y Register
PC uint16 // Program Counter
SP uint8 // Stack Pointer
Status uint8 // Status Flags
Bus Bus // Connection to the Bus
}
func (c *CPU) Reset() {
c.A = 0
c.X = 0
c.Y = 0
c.SP = 0xFD
c.Status = 0x24
c.PC = 0x0000
}
// Small helper func to flip the status register bits
func (c *CPU) setFlag(flag uint8, set bool) {
if set {
c.Status |= flag
} else {
c.Status &= ^flag
}
}
// fetch -> decode -> execute cycle
func (c *CPU) Step() {
// fetch with program counter and bus memory
opcode := c.Bus.Read(c.PC)
fmt.Printf("Executing at PC: %04X | Opcode: %02X\n", c.PC, opcode)
// decode + exe need to split this out to handle all instructions etc
// Look at : https://www.ahl27.com/posts/2023/01/6502-emu1/
switch opcode {
case 0xEA: //NOP
// does nothing its a no op
default:
fmt.Printf("Unknown opcode: %02X\n", opcode)
}
// Move the Program counter
c.PC++
}